--
-- VHDL Architecture vga_lib.hsync.arch
--
-- Created:
--          by - andax656.student (southfork-12.edu.isy.liu.se)
--          at - 10:24:09 10/05/11
--
-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.numeric_std.all;

ENTITY hsync IS
   PORT( 
      fpga_clk     : IN     std_logic;
      fpga_reset_n : IN     std_logic;
      vga_clk      : IN     std_logic;
      hblank       : OUT    std_logic;
      vga_hsync_n  : OUT    std_logic;
      pcnt         : IN     integer RANGE 0 TO 794
   );

-- Declarations

END hsync ;

--
ARCHITECTURE arch OF hsync IS
BEGIN
  process(fpga_clk)
  begin
    if rising_edge(fpga_clk) then
      
      if fpga_reset_n = '0' then
        vga_hsync_n <= '1';
        
      elsif vga_clk = '1' then
      -- runs every 0,04 us
         
        if pcnt <= 655 then 
          vga_hsync_n <= '1';
        elsif pcnt <= 750 then
          vga_hsync_n <= '0';
        else
          vga_hsync_n <= '1';
        end if;
          
        --hblank = 1 after 640 pix are displayed
        if pcnt <= 640 then
          hblank <= '0';
        else
          hblank <= '1';
        end if;
           
      end if;
    end if;
  end process;
END ARCHITECTURE arch;

